1. Field of the Invention
The present invention relates to a reference signal generating circuit that generates a reference signal which is compared with an analog signal at the time of AD conversion. Furthermore, the present invention relates to an AD conversion circuit and an imaging device which include the reference signal generating circuit.
Priority is claimed on Japanese Patent Application No. 2012-284605, filed Dec. 27, 2012, the content of which is incorporated herein by reference.
2. Description of Related Art
As an example using a reference signal generating circuit according to a related art, there is an imaging device. Japanese Unexamined Patent Application, First Publication No. 2011-250009 discloses an imaging device in which an AD conversion circuit (ADC) is arranged for each pixel column. FIG. 9 illustrates an exemplary constitution of an imaging device which is almost the same to the imaging device disclosed in Japanese Unexamined Patent Application, First Publication No. 2011-250009. A solid state imaging device 1001 illustrated in FIG. 9 includes an imaging unit 1002, a read current source unit 1005, an analog unit 1006, a reference signal generating circuit 1010, a vertical selecting unit 1012, a horizontal selecting unit 1014, an ADC group 1015, an output unit 1017, and a control unit 1020.
The imaging unit 1002 includes a photodiode (a photoelectric conversion element) and an intra-pixel amplifier, and unit pixels 1003, each of which outputs a pixel signal according to the amount of an incident light are arranged in the form of a matrix. The control unit 1020 is a control circuit that reads a pixel signal from the imaging unit 1002 and performs AD conversion on the read pixel signal. The vertical selecting unit 1012 performs control of a row address or row scanning of the imaging unit 1002 through a row control line 1011. The horizontal selecting unit 1014 performs control of a column address or column scanning of the ADC group 1015. The read current source unit 1005 is a current source that reads a pixel signal from the imaging unit 1002 as a voltage signal. The analog unit 1006 performs amplification and the like as necessary.
The reference signal generating circuit 1010 includes a clock generating unit 1018 and a ramp wave generating unit 1019, and generates a ramp wave as a reference signal whose voltage value increases or decreases with the passage of time. The clock generating unit 1018 includes a voltage-controlled oscillator (VCO) 1018a, and generates a clock signal used to drive the ramp wave generating unit 1019 based on a pulse signal applied from the control unit 1020. The ramp wave generating unit 1019 generates the ramp wave based on the clock signal applied from the clock generating unit 1018.
The ADC group 1015 has column ADC units 1016 which is arranged for each of vertical signal line 1013 corresponding to a pixel column. The column ADC units 1016 has an n-bit (n is a natural number of 2 or more) digital signal conversion function. The column ADC unit 1016 constitutes an analog-digital conversion means (AD conversion circuit) that converts an analog pixel signal read from the unit pixel 1003 of a selected pixel row of the imaging unit 1002 into digital pixel data together with the reference signal generating circuit 1010.
The column ADC unit 1016 includes a comparing unit 1109, a latch unit 1108, a counter 1103, and a memory unit 1104. The comparing unit 1109 compares the ramp wave from the reference signal generating circuit 1010 with the analog signal obtained through each vertical signal line 1013 from the unit pixel 1003 for each row control line 1011. The latch unit 1108 includes a latch circuit that latches (holds/stores) a logical state of a low-order phase signal composed of a plurality of clock signals output from the clock generating unit 1018. The counter 1103 counts one of the clock signals configuring the low-order phase signal as a count clock. The comparing unit 1109 compares the ramp wave with the analog signal during a period of time corresponding to a voltage of a pixel signal, and a result of measuring the period of time is obtained as data of the logical state of the low-order phase signal latched by the latch unit 1108 and data of a result of counting through the counter 1103.
The data latched by the latch unit 1108 and the counter 1103 is transferred to the memory unit 1104. The memory unit 1104 is connected to a horizontal transfer line 1021. The output unit 1017 includes a sense amplifier circuit, performs binarization and subtraction on data output to the horizontal transfer line 1021, and outputs final AD conversion result data to the outside of the imaging device 1001.
Next, an operation of the imaging device 1001 will be described. As analog pixel signals read from the unit pixels 1003 of a selected row of the imaging unit 1002, a reset level including noise of a pixel signal is read during a first read operation, and then a signal level is read during a second read operation. Then, the reset level and the signal level are input to the ADC group 1015 in time series through the vertical signal line 1013.
After the first read operation from the unit pixels 1003 of an arbitrary row to the vertical signal line 1013 is stabilized, the ramp wave (reference signal) obtained by temporally changing a reference voltage is generated by the reference signal generating circuit 1010 and input to the comparing unit 1109. The comparing unit 1109 compares a voltage of the ramp wave with a voltage of the analog signal of the vertical signal line 1013. In parallel with input of the ramp wave to the comparing unit 1109, a first count is performed by the counter 1103.
When a relationship representing whether the voltage of the ramp wave is higher or lower than the voltage of the analog signal of the vertical signal line 1013 is reversed, an output of the comparing unit 1109 is inverted, and at the same time, data corresponding to a period of time during which the comparing unit 1109 performs a comparison is latched in the latch unit 1108 and the counter 1103. When the first read operation is performed, since a variation in the reset level of the unit pixel 1003 is usually small and a reset voltage is common to all pixels, a voltage of the analog signal output to an arbitrary vertical signal line 1013 is approximately equal to a known value. Thus, when the first read operation is performed, the comparison period of time can be reduced by appropriately adjusting the voltage of the ramp wave. The data latched in the latch unit 1108 and the counter 1103 is transferred to the memory unit 1104.
When the second read operation is performed, in addition to the reset level, a signal level of each unit pixel 1003 corresponding to the amount of an incident light is read, and the same operation as in the first read operation is performed. In other words, when the second read operation from the unit pixels 1003 of an arbitrary row to the vertical signal line 1013 is stabilized, the ramp wave is generated by the reference signal generating circuit 1010 and then input to the comparing unit 1109. The comparing unit 1109 compares a voltage of the ramp wave with a voltage of the analog signal of the vertical signal line 1013. In parallel with input of the ramp wave to the comparing unit 1109, a second count is performed by the counter 1103.
When a relationship representing whether the voltage of the ramp wave is higher or lower than the voltage of the analog signal of the vertical signal line 1013 is reversed, an output of the comparing unit 1109 is inverted, and at the same time, data corresponding to a period of time during which the comparing unit 1109 performs a comparison is latched in the latch unit 1108 and the counter 1103. The data latched in the latch unit 1108 and the counter 1103 is transferred to the memory unit 1104.
After the second read operation ends, the first data and the second data held in the memory unit 1104 are detected by (the sense amplifier circuit of) the output unit 1017 via the horizontal transfer line 1021 through the horizontal selecting unit 1014. Then, in the output unit 1017, binarization of the data latched in the latch unit 1108 is performed, and the data obtained in the first read operation is subtracted from the data obtained in the second read operation, and then the subtracted data is output to the outside. Thereafter, the same operation is sequentially performed for each row, and thus a two-dimensional image is generated. The binarization and the subtraction may be performed in the column ADC unit 1016.
A reference signal generating circuit of an imaging device employing an AD conversion circuit of a time to digital converter (tdc) type single slope (SS) generates the ramp wave (reference signal) using an annular delay circuit. This is because a circuit size can be reduced by using an output of an annular delay circuit as both a low-order phase signal for a latch and a signal for ramp wave generation.